LSI design system

ABSTRACT

Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates to an improvement of an LSI design systemusing a computer, and more particularly to an LSI design system which iscapable of preventing the occurrence of voltage drop and noise which arecaused by the concentration of cells or wirings.

[0003] 1. Description of the Related Arts

[0004] Recently, along with the advancement of the fine processingtechnology, the high integration of the LSI has been progressed andhence, the demand for further speedup or further lowering of voltages ofan LSI and the demand for the development of an LSI in a short periodare increasing.

[0005] In designing the densely packed cells and wirings, voltage dropand noise occur due to the partial concentration of consumed power andthis causes the malfunction of the LSI and lowering of the yield. Thisis caused by a following reason. That is, the voltage drop occurs incase the consumed power of the cells connected to power trunks isrelatively large compared to the power supplied to the power trunks.When the voltage drop occurs, there arises a problem that driving ofcells connected to the power trunks requires a long time or cells becomeinoperable. On the other hand, noise occurs in the following manner.That is, when signals are changed approximately in the identical timingat a plurality of neighboring wirings, a capacitance constructed betweenwires mediates unexpected signal as noise. This noise causes the delayor rashness of the signal.

[0006] As illustrated in FIG. 23, when a plurality of cells having alarge consumed power, for example, cells which are given instance namesA-D are arranged in such a manner that they are concentrated at oneplace, voltage drop occurs thus giving rise to a malfunction of acircuit.

[0007] Conventionally, the layout of wirings has been designed in such amanner that the wirings are arranged without taking change of signalsinto account. With respect to three wirings N1, N2, N3 illustrated inFIG. 24 which generate change of signals, when two wirings N1, N2 whichgenerate change of signals in the identical timing are arranged close toeach other as shown in FIG. 25, noise occurs thus giving rise to amalfunction of the circuit.

[0008] Conventionally, based on information on an arrangement of cellsand wirings obtained after designing the layout, in case voltage drop isgreater than the minimum operating voltage, the cells which aresubjected to such a voltage drop are rearranged so as to ensure theminimum operating voltage thus preventing the voltage drop. One exampleof such method has been disclosed in Japanese laid-open patentpublication Hei 9-130622, the U.S. Pat. No. 5,598,348 and the U.S. Pat.No. 5,751,957.

[0009] Furthermore, considering the necessity of preventing theoccurrence of noise, with respect to wirings which are arranged inparallel to each other, it has been recommended to set a wide spacingbetween wirings from the beginning.

[0010] The rearrangement of cells after completion of the designing ofthe layout requires considerable efforts and time. Furthermore, in casethe rearrangement of cells turns out to be insufficient to preventvoltage drop, the layout of the entire circuit must be designed again.Such a redesigning of the layout prolongs the development period of theLSI.

[0011] Setting of the wide spacing or distance between wirings from thebeginning to obviate such troubles, on the other hand, increases thearea of the LSI, gives rise to an increase of cost and makes the highintegration of the LSI difficult.

SUMMARY OF THE INVENTION

[0012] Accordingly, it is a primary object of the present invention toprovide an LSI design system which can prevent voltage drop withoutnecessitating rearranging of cells after designing of a layout,redesigning of an entire circuit, or setting of a wide spacing betweenwirings.

[0013] It is another object of the present invention to provide an LSIdesign system which can prevent the occurrence of noise withoutnecessitating rearranging of cells after designing of a layout,redesigning of an entire circuit, or setting of a wide spacing betweenwirings.

[0014] To achieve the above objects, the LSI design system of thepresent invention is constructed by including separation informationgenerating means which generates information on cells to be separatedwhich require a separate arrangement from each other based on therelative comparison of respective consumed powers of cells which aresubjected to a layout, and layout generating means which generates alayout based on the information.

[0015] The cells to be separated which have to be arranged in aspaced-apart manner are arranged in a spaced-apart manner from thebeginning of an layout based on the information of the separationinformation generating means.

BRIEF DESCRIPTION OF THE DRAWING

[0016] The other objects of the present invention will be made clear asembodiments which will be explained hereinafter are understood, and theyare explicitly described in attached claims. Furthermore, many otheradvantages which will not be discussed in this specification will bereadily understood by those who are skilled in the art once the presentinvention is reduced into practice.

[0017]FIG. 1 is an explanatory view illustrating an LSI designing systemaccording to the first preferred embodiment of the present invention.

[0018]FIG. 2 is an explanatory view illustrating the content of cellconnection information and cell consumed power information.

[0019]FIG. 3 is an explanatory view illustrating the content ofseparation information.

[0020]FIG. 4 is an explanatory view illustrating the arrangementcondition of cells which constitutes a generated layout.

[0021]FIG. 5 is an explanatory view illustrating the content ofseparation information according to a modification 2.

[0022]FIG. 6 is an explanatory view showing a layout according to themodification 2.

[0023]FIG. 7 is an explanatory view illustrating the consumed power ofevery interval according to a modification 3.

[0024]FIG. 8 is an explanatory view illustrating numerical examples ofthe consumed power of every time zone.

[0025]FIG. 9 is an explanatory view illustrating the content ofseparation information according to the modification 3.

[0026]FIG. 10 is an explanatory view explaining an LSI design systemaccording to the second preferred embodiment of the present invention.

[0027]FIG. 11 is an explanatory view illustrating grouped cells forseparation.

[0028]FIG. 12 is an explanatory view illustrating the content ofseparation information.

[0029]FIG. 13 is an explanatory view illustrating a cell arrangementwhich constitutes a generated layout.

[0030]FIG. 14 is an explanatory view explaining an LSI design systemaccording to the third preferred embodiment of the present invention.

[0031]FIG. 15 is an explanatory view illustrating the content ofseparation information.

[0032]FIG. 16 is an explanatory view illustrating an arrangementcondition of wirings which constitutes a generated layout.

[0033]FIG. 17 is an explanatory view explaining an LSI design systemaccording to the fourth preferred embodiment of the present invention.

[0034]FIG. 18 is an explanatory view illustrating wirings contained incell connection information.

[0035]FIG. 19 is an explanatory view explaining numerical examples ofjunction numbers which respective wirings have.

[0036]FIG. 20 is an explanatory view explaining the content ofseparation information.

[0037]FIG. 21 is an explanatory view illustrating an arrangementcondition of wirings which constitutes a generated layout.

[0038]FIG. 22 is an explanatory view illustrating the content of theseparation information according to a modification 4.

[0039]FIG. 23 is an explanatory view illustrating a layout generated bya conventional LSI design system.

[0040]FIG. 24 is an explanatory view illustrating the signal changecondition of wirings.

[0041]FIG. 25 is an explanatory view illustrating the generated layout.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0042] Preferred embodiments of this invention are explained in detailin conjunction with attached drawings.

[0043] An LSI design system according to the first preferred embodimentof the present invention, as illustrated in FIG. 1, includes separationinformation generating means S1, layout generating means S2 and layoutstoring means S3. The separation information generating means S1generates separation information I3 from cell connection information I1and cell consumed power information I2 which is contained in the cellconsumed power information I1. The cell consumed power information I2 ismainly composed of consumed powers of respective cells. Here, as theconsumed power, the dynamic consumed power is used, for example. Theseparation information I3 is information on a pair of separate cells,that is, a pair of cells which are to be arranged separately or in aspaced-apart manner at the time of generating a layout. The layoutgenerating means S2 constitutes means which generates the layout basedon the separation information I3. The layout storing means S3 stores thelayout generated by the layout generating means S2. Although not shownin drawings, a display unit which displays the generated layout maypreferably be provided. Furthermore, in case the generated layout isoutputted and stored in an external storing device, the layout storingmeans S3 is not necessary specifically.

[0044] In this LSI design system, when the cell connection informationI1 and the cell consumed power information I2 are inputted, theseparation information generating means S1 generates the separationinformation I3. Then, the layout generating means S2 generates thelayout in which a pair of separate cells which constitute the separationinformation I3 are arranged separately or in a spaced-apart manner. Thegenerated layout is stored in the layout storing means S3.

[0045] Here, the manner of generating the layout is specificallyexplained in view of FIG. 2-FIG. 4.

[0046] The cell connection information I1 and the cell consumed powerinformation I2 are respectively composed of twelve cells which are giveninstance names A-L respectively as shown in FIG. 2, for example. Theaverage of the consumed powers of these cells (hereinafter called ascell average) is 0.2. The cells which have the consumed power largerthan the cell average 0.2 are four cells made of four cells A, B, C andD.

[0047] When the cell connection information I1 and the cell consumedpower information I2 are inputted, the separation information generatingmeans S1 extracts the cells A, B, C and D which have the consumed powerlarger than the cell average as cells to be separated, wherein the cellaverage of 0.2 is set as a threshold value. Then, as shown in FIG. 3,the separation information generating means S1 generates separationinformation I3 in which combinations (A,B), (A,C), (A,D), (B,C), (B,D),(C,D) are prepared by takes out an arbitrary pair from cells A, B, C, Dto be separated and these combinations are generated as pairs ofseparate cells. These pairs of separate cells are generated on allpossible combinations made of cells to be separated. It is judged thatcells to be separated are not present in case the extracted cell to beseparated is one.

[0048] Based on the separation information I3, the layout generatingmeans S2 generates the layout where respective pairs of separate cellsare arranged separately or in a spaced-apart manner from each other. Tobe more specific, the layout is generated in such a manner that betweencells to be separated, at least one of cells E-L which are not cells tobe separated is arranged. Due to such a construction, in each pair ofseparate cells, the cells to be separated which constitute each pair ofseparate cells are arranged in a spaced-apart manner from each other. Anexample of such a layout is shown in FIG. 4.

[0049] According to this LSI design system, an arrangement that cells A,B, C, D to be separated which respectively have a large consumed powerare arranged in a concentrated manner at a part can be obviated.Eventually, voltage drop which is caused by the uneven distribution ofparts which have a large consumed power can be prevented. Furthermore,the layout which can prevent the voltage drop can be set at the time ofgenerating an initial layout. Accordingly, an LSI which ensures areliable operation thereof can be developed in a short period.Furthermore, the malfunction of an LSI or lowering of the yield can besuppressed preliminarily.

[0050] An example of this LSI design system is not limited to theabove-mentioned construction and the LSI design system can adoptsfollowing constructions of modifications 1-3.

[0051] Modification 1 is characterized by altering a portion of theseparation information generating means S1. In this modification 1, theseparation information generating means S1 generates the separationinformation I3 in the following manner.

[0052] Based on the consumed power information, the consumed power ofeach cell A-L and the sum of consumed powers of respective cells A-L(hereinafter called as ‘cell sum’) are compared. In case the ratio ofconsumed power of each cell A, B, C, D relative to the cell sum exceedsa preset threshold value (for example, 10%), these cells are determinedas cells to be separated. Pairs of separate cells which are made ofcombinations of these cells to be separated are extracted and theseparation information I3 made of these pairs of separate cells isgenerated.

[0053] In the modification 1, although the threshold value forextracting pairs of separate cells is set to 10% of the cell sum as anexample, this threshold value is not necessarily 10% and can be set toany arbitrary value. From the experience, it has been found that it isproper to set the threshold value within a range of 1%-10% of the cellsum.

[0054] Modification 2 is also characterized by altering a portion of theseparation information generating means S1. In this modification 2,along with the alteration of the separation information generating meansS1, the separation information I3 and the layout generating means S2 arealso altered partially. This separation information generating means S1generates the separation information I3 in the following manner.

[0055] This separation information generating means S1 sets theabove-mentioned cell average 0.2 as a threshold value and the cell A, B,C, D whose consumed power exceeds the cell average is determined as thecell to be separated and the combinations of cells A, B, C, D to beseparated are extracted as pairs of separate cells.

[0056] In the example of FIG. 2 in which four cells A, B, C, D to beseparated are extracted, the pairs of separate cells are constituted by(A,B), (A,C), (A,D), (B,C), (B,D), (C,D) as shown in FIG. 5.

[0057] On each pair of separate cells, a combined value of consumedpower (hereinafter called as ‘pair combined value’) is calculated and aseparation distance which is directly proportional to the pair combinedvalue is set as separation distance information of this pair of separatecells. The separation information generating means S1 uses thecalculated pair of separate cells and the separation distanceinformation as the separation information I3.

[0058] For example, in case of the pair of separation cells (A,B), sincethe consumed power of the cell A is 0.5 and the consumed power of thecell B is 0.5, the pair combined value becomes 0.5+0.5=1.0. Theseparation distance information is calculated by multiplying the paircombined value with a coefficient N greater than 0, for example. In FIG.5, as an example, by setting the coefficient N to 10, the separationdistance information of 10.0 is calculated.

[0059] As shown in FIG. 6, the layout generating means S2 generates alayout in such a manner that respective pairs of separate cells whichare defined by the separation information I3 are arranged remoter thanthe separation distance information. The distance unit which theseparation distance information indicates can be set to various values.

[0060] It is also possible to combine the modification 1 with themodification 2. In this case, the separation information generatingmeans S1 extracts the cells whose ratio of consumed power relative tothe cell sum exceeds a given threshold value (10%, for example) as thecells to be separated. Thereafter, the separation distance informationof the pairs of separate cells is calculated in the same manner as themodification 2.

[0061] Modification 3 is also characterized by the separationinformation generating means S1 having a portion thereof modified. Thisseparation information generating means S1 generates the separationinformation I3 in the following manner.

[0062] First of all, in every time zone defined by a given timeinterval, a time zone consumed power of each cell (hereinafter called as‘time zone cell consumed power’) and a combined value of time zoneconsumed powers of all cells (hereinafter called as ‘time zone combinedvalue’) are calculated. Furthermore, the average of the calculated timezone consumed powers of respective cells (hereinafter called as celltime zone average) and the average of time zone combined values(hereinafter called as ‘combined value time zone average’) are obtained.

[0063] Then, the time zone whose time zone combined value is larger thanthe combined value time zone average is extracted as an object timezone. The time zone cell consumed powers of respective cells and thecell time zone average in each extracted object time zone are comparedand it is judged whether a plurality of cells which have the time zonecell consumed power greater than the cell time zone average are presentwithin one object time zone or not. If one or no such cell is present,it is judged that the cell to be separated is not present. On the otherhand, if a plurality of these cells are present, a pair of cells to beseparated are extracted from these cells so as to generate a pair ofseparate cells. A pair of separate cells is generated with respect toall pairs of cells which can be set. A pair of separate cells aregenerated with respect to all object time zones.

[0064] On each pair of separate cells as determined, the time zone paircombined value is calculated and distance information which is directlyproportional to the time zone pair combined value is set as theseparation distance information of the object time zone. Setting of theseparation distance information is performed in the same manner as inthe case of the modification 2. In the modification 3, the separationinformation I3 is composed of the separation distance information andthe pairs of separate cells.

[0065] In case the same pair of separate cells is present in differentobject time zones, the separation distance information having the largervalue is chosen as the separation distance information of the pair ofseparate cells.

[0066] The manner of generating the separation information according tothe modification 3 is specifically explained in view of FIG. 7. In FIG.7, the cells E-L which have small time zone cell consumed powers andaccordingly give little influence to generating of the layout areomitted from the drawing.

[0067] In every time zone t1-t6 which is set to an arbitrary timeinterval, the time zone combined value is calculated. The time zone cellconsumed power of each cell A-D of every time zone t1-t6 is calculated.In FIG. 7, time is taken on abscissa and the consumed power is taken onordinate. Symbols A-D show the instance name of the cells.

[0068] Calculated time zone cell consumed power and calculated time zonecombined value are put in order and are shown as a graph in FIG. 8. Thetime zone combined value is 40 in the time zone t1, 15 in the time zonest2 and t3, 10 in the time zone t4, 30 in the time zone t5 and 55 in thetime zone t6. The combined value time zone average is 27.5, while thecell time zone average is 10.3.

[0069] The time zones t1, t5, t6 which have the time zone combined valuegreater than the combined value time zone average 27.5 are extracted asobject time zones. Among the object time zones t1, t5, t6, the time zonet6 in which a plurality of cells whose time zone cell consumed powerexceeds the cell time zone average 10.3 are present is set as the finalobject time zone. In this object time zone t6, the cells to be separatedare A and B, while a pair of separate cells is (A,B).

[0070] The time zone pair combined value of the pair of separate cells(A,B) at the object time zone t6 is 45 and the separation distanceinformation is obtained by multiplying the coefficient N to this timezone pair combined value. In the construction of the modification 3, theseparation distance information is calculated based on the time zonepair combined value and hence, it is unnecessary to set the largecoefficient N and it is proper to set the coefficient to 1. In thiscase, the separation distance information becomes 45.

[0071] The separation information I3 of the modification 3 is composedof a pair of separate cells (A,B) and the separation distanceinformation. The separation information I3 of the modification 3 isshown in FIG. 9.

[0072] As explained above, in this modification 3, the time zones whosetime zone combined value is greater than the combined value time zoneaverage are set as the object time zones and among the object timezones, the combination of cells whose time zone cell consumed power isgreater than the cell time zone average is set as a pair of separatecells. The present invention, however, is not limited to such aconstruction. That is, the time zone combined values of every time zoneare calculated and these time zone combined values are summed in alltime zones, and the time zones whose ratio of time zone combined valuerelative to the sum exceeds a given threshold value may be extracted asthe object time zones. In this case, from the experience, it has beenfound that such a given threshold value should preferably be 1-10%.

[0073] Among extracted object time zones, the cells whose ratio of timezone cell consumed power relative to the above-mentioned cell sumexceeds a given threshold value is determined as the cells to beseparated and the combination of these cells to be separated isextracted as a pair of separate cells. In this case, from theexperience, it has been found that such a given threshold value shouldpreferably be 1-10%. The separation information I3 is generated bysetting the pair combined value of the extracted pair of separate cellsas the separation distance information of the object interval.

[0074] Subsequently, the LSI design system according to the secondpreferred embodiment of the present invention is explained hereinafter.As illustrated in FIG. 10, this LSI design system includes divisioninformation generating means S11, layout generating means S12 and layoutstoring means S13.

[0075] The division information generating means S11 generates celldivision information I13 from cell connection information I1 and cellconsumed power information I2 contained in the cell connectioninformation I1 at the time of generating a layout. Layout generatingmeans S12 generates the layout based on the division information I13generated by the division information generating means S11. Layoutstoring means S13 stores the generated layout.

[0076] In this LSI design system, first of all, the number of divisionof the whole cells is set. Then, an evaluation function is calculated bydividing the cell sum explained in the embodiment 1 with the number ofdivision. The evaluation function has a following meaning. That is,assuming that the whole cells are divided by the set number of division,the evaluation function means the average of the combined value ofconsumed powers of respective cell groups which are grouped by such adivision. The cell groups are hereinafter simply called as groups, whilethe combined value of consumed powers of each cell group is called asthe group combined value.

[0077] Based on the calculated evaluation function, the whole cells aredivided by the above-mentioned number of division so as to generaterespective groups. Here, cells which constitute each group is selectedsuch that the group combined value of each group agrees with theevaluation function as exactly as possible. Accordingly, there is nopossibility that the consumed power of each group unit is increased in aprotruding manner partially so that the group combined value isequalized among groups.

[0078] The division information I13 which is composed of theabove-mentioned group division information of cells is generated by theexecution of the division information generating means S11. The layoutgenerating means S12 arranges respective cells of every group based onthe division information I13.

[0079] The manner of operation of this example is specifically explainedhereinafter. Here, the content of the cell connection information I1 andthe cell consumed power information I2 are similar to those ofcounterparts shown in FIG. 2 and the explanation is made provided thatthese cells are grouped into four groups.

[0080] The evaluation function which equalizes the cell sum 2.4 in fouris 0.6. Then, the division information generating means S11 to which thecell connection information I1 and the cell consumed power informationI2 are inputted divides respective cells into respective groupsillustrated in FIG. 11 based on the evaluation function 0.6. By dividingcells into respective groups, the division information I13 illustratedin FIG. 12 is generated.

[0081] The layout generating means S12 generates a layout illustrated inFIG. 13 based on the division information I13. As a result, the layoutwhere cells are divided into a plurality of groups which consumesubstantially equal power is obtained.

[0082] According to the LSI design system of this embodiment, as in thecase of the first embodiment, the concentrated arrangement of cellshaving large consumed powers can be obviated and hence, voltage dropcaused by the uneven distribution of the parts having large powerconsumption can be prevented. Furthermore, the layout which can preventvoltage drop can be generated at the time of generating an initiallayout. Accordingly, the LSI which ensures a reliable operation thereofcan be developed in a short period. Furthermore, a malfunction of theLSI and lowering of the yield can be suppressed in advance.

[0083] Subsequently, the LSI design system of the third preferredembodiment of the present invention is explained hereinafter. The LSIdesign system of this embodiment is characterized in that information onwirings which are to be arranged separately or in a spaced-apart manneris generated and based on the information, the wiring are arrangedseparately.

[0084] This LSI design system, as shown in FIG. 14, includes separationinformation generating means S21, layout generating means S22 and layoutstoring means S23. The separation information generating means S21extracts a pair of wirings which have signal changing points whichchange in the equal timing each other (hereinafter called as ‘wirings tobe separated’) from the cell connection information I1 and wiringoperation information I22 included in the cell connection informationI1. Then, the separation information I23 which is composed of a pair ofextracted wirings to be separated. The separation information I23 isgenerated in such a manner that the separation information I23 includesall pairs of wirings which constitute pairs of wirings to be separated.

[0085] The layout generating means S22 generates a layout based on theseparation information I23 which is generated by the separationinformation generating means S21.

[0086] In this embodiment, the layout is generated in such a manner thatno noise occurs between wirings. That is, when the change of signalsoccurs between neighboring wirings in the equal timing, a capacitance isgenerated between the wirings and due to this capacitance, the delay orthe rashness of the signal occurs and hence, noise occurs. Accordingly,in this embodiment, the layout is generated such that the wirings whichgenerate the change of signals in the equal timing are not arrangedclose to each other so as to prevent the occurrence of noise. Betweenneighboring wirings, not only a point of change of signal of the samephase but also a point of change of signal of the anti-phase becomes thecause of noise and hence, irrespective of the phase, a pair of wiringswhich have the a point of change of signal occurring in the equal timingare set as a pair of wirings to be separated.

[0087] Hereinafter, the operation of this embodiment is specificallyexplained. The cell connection information I1 includes the wiringoperation information I22 of three wirings N1, N2, N3 which generate thechange of signal as illustrated in FIG. 24 in the same manner as theprior art. In FIG. 24, time is taken on abscissa and symbols {circleover (1)}, {circle over (2)}, {circle over (3)} indicated in the drawingrespectively indicate time zones which are divided at given timeintervals respectively. In FIG. 24, the wiring N1 and the wiring N2 havethe points of change of signal of the equal timing and hence, theseparation information generating means S21 generates the separationinformation I23 shown in FIG. 15 which sets a combination of the wiringsN1, N2 as a pair of wirings to be separated.

[0088] Based on the separation information I23, the layout generatingmeans S22 generates a layout which arranges the wirings N1, N2 to beseparated included in a pair of wirings to be separated in aspaced-apart manner from each other. That is, the layout generatingmeans S22 generates a layout shown in FIG. 16, for example.

[0089] As a result, the wirings N1, N2 to be separated are arranged in aspaced-apart manner while sandwiching the wiring N3 which is not awiring to be separated. In the LSI design system according to thisembodiment, even when the wirings N1, N2, N3 are arranged parallel toeach other, an advantage that an LSI having the least noise can bedeveloped in a short period is obtained.

[0090] In FIG. 24, the wirings N1, N2 to be separated change the signalsin the equal timing not only at the signal change start point but alsoat the signal change end point. However, it is needless to say that thewirings N1, N2 can be set as wirings to be separated which constitute apair of wirings to be separated so long as the change of signals isgenerated in the equal timing at either one of the signal change startpoint or the signal change end point. Furthermore, it is needless to saythat when the signal change start point of one wiring and the signalchange end point of the other wiring take place in the equal timing,these wirings can be set as wirings to be separated which constitute apair of wirings to be separated

[0091] Subsequently, the fourth preferred embodiment of the presentinvention is hereinafter explained. As shown in FIG. 17, a LSI designsystem according to this embodiment includes separation informationgenerating means S31, layout generating means S32 and layout storingmeans S33. The separation information generating means S31 generatesseparation information I33 from the cell connection information I1. Thelayout generating means S32 generates a layout which arranges wirings ina spaced-apart manner based on the separation information I33 generatedby the separation information generating means S31.

[0092] Among wirings which are included in the cell connectioninformation I1, the separation information generating means S31 sets thewirings having the junction number which is equal to or exceeds a giventhreshold value as the wirings to be separated. The above-mentionedthreshold value is determined based on the average of junction number ofthe wiring, for example. Usually, the average of the junction number isabout 2-3 and hence, it is proper to set the value of the thresholdvalue to about 5-10 which is slightly larger than 2-3. In thisembodiment, the junction number 10 is set as the threshold value in viewof the experience.

[0093] This embodiment is specifically explained hereinafter in view acase that the cell connection information I1 includes wirings N1-N8 asillustrated in FIG. 18 and the wirings to be separated having thejunction number of not less than 10 are set to (N4, N5, N6) asillustrated in FIG. 19, for example.

[0094] In this case, as shown in FIG. 20, the separation informationgenerating means S31 generates the separation information I33 which iscomposed of the wirings to be separated (N4, N5, N6). The layoutgenerating means S32 arranges these wirings to be separated (N4, N5, N6)in a spaced-apart manner from each other. For example, the layoutgenerating means S32 generates a layout shown in FIG. 21. That is, thelayout is generated in such a manner that at least one of wirings N1,N2, N3, N7, N8 which are not included in the wirings to be separated issandwiched between the wirings to be separated which constitute thewirings to be separated (N4, N5, N6).

[0095] This LSI design system obviates the concentrated arrangement ofthe wirings having a large consumed power and enables the prevention ofvoltage drop which is caused by a partial power consumption at the timeof an initial layout.

[0096] The LSI design system of this embodiment is not limited to theabove-mentioned construction. The LSI design system also includes afollowing modification 4 although it is not shown in drawings. Themodification 4 is characterized by modifying a portion of the separationinformation generating means S31. Along with the modification of thisseparation information generating means S31, the modification 4 differfrom the above-mentioned embodiment also in view of the separationinformation I33 and the layout generating means S32.

[0097] This modification 4 is explained in view of a wiring arrangementshown in FIG. 18 and FIG. 19 as an example. The separation informationgenerating means S31 of the modification 4 extracts pairs of wirings tobe separated (N4, N5), (N4, N6), (N5, N6) which are composed ofcombinations of the wirings to be separated included in the wirings tobe separated (N4, N5, N6) and calculates a combined value of junctionnumbers of wirings to be separated on every pair of wirings to beseparated. Then, the distance which is directly proportional to thejunction number combined value is determined as the separate distanceinformation and the separation information I33 which is composed of thepairs of wirings to be separated and the separation distance informationis generated. To be more specific, the separation information generatingmeans S31 generates the separation information I33 illustrated in FIG.22.

[0098] The layout generating means S32 generates a layout based on thepairs of wirings to be separated and the separation distance informationincluded in the separation information I33. Accordingly, the layoutsimilar to the layout shown in FIG. 21 can be generated.

[0099] As has been described heretofore, respective LSI design systemsof the present invention can satisfy the demand for further speedup orfurther lowering of voltage and the demand for the development in ashort period, and furthermore, can prevent the occurrence of noise andvoltage drop caused by the concentration of the power consumption at apart. Accordingly, it is no more necessary to rearrange cells or to forma layout of the entire circuit again after generating an initial layout.Furthermore, it is no more necessary to set a wide spacing betweenwirings so that the high integration of the LSI can be easily realized.

[0100] Although the present invention has been explained in detail inview of the most preferred embodiments, the combinations and thearrangements of the components of such preferred embodiments can bealtered in various forms without departing from the spirit and the scopeof the present invention as claimed later.

What we claim is:
 1. An LSI design system comprising; separationinformation generating means which generates separation information oncells to be separated which are to be arranged in a spaced-apart mannerfrom each other based on a relative comparison of respective consumedpowers of cells which are subjected to a layout, and layout generatingmeans which generates a layout based on said separation information. 2.An LSI design system according to claim 1, wherein said layoutgenerating means generates a layout having an arrangement that at leastone cell whose separation is not necessary is sandwiched between saidcells to be separated.
 3. An LSI design system according to claim 1,wherein said separation information generating means generates saidseparation information which determines cells which consume powergreater than an average of consumed powers of all cells as said cells tobe separated.
 4. An LSI design system according to claim 1, wherein saidseparation information generating means generates said separationinformation which sets cells whose ratio of consumed power per a cellunit relative to the sum of consumed powers of all cells is greater thana preset threshold value as said cells to be separated.
 5. An LSI designsystem according to claim 1, wherein said separation informationgenerating means calculates a time zone consumed power of each cell anda combined value of time zone consumed powers of all cells of every timezone divided to a preset time interval, and calculates an average ofsaid calculated time zone consumed power of each cell and said combinedvalue of time zone consumed powers of all cells, extracts said timezones whose combined value of time zone consumed powers of all cells isgreater than the average thereof as object time zones, and generatesseparation information which sets cells whose each time zone consumedpower is greater than the average thereof as said separation cells insaid extracted object time zones.
 6. An LSI design system according toclaim 1, wherein said separation information generating means generatessaid separation information which includes separation distanceinformation between said cells to be separated.
 7. An LSI design systemaccording to claim 6, wherein said separation information generatingmeans generates distance information which is directly proportional to acombined value of consumed powers of said cells to be separated as saidseparation distance information.
 8. An LSI design system comprising;division information generating means which generates divisioninformation which divides all cells to be subjected to a layout into aplurality of groups which have substantially equal consumed powers, andlayout generating means which generates a layout arranged per each groupunit based on said division information generated by said divisioninformation generating means.
 9. An LSI design system comprising;separation information generating means which generates information onwirings to be separated which are to be spaced apart from each otherbased on a comparison of signal operation timing information ofrespective wirings which are subjected to a layout, and layoutgenerating means which generates a layout based on said separationinformation.
 10. An LSI design system according to claim 9, wherein saidlayout generating means generates a layout which arranges at least onewiring which is unnecessary to be separated between said wirings to beseparated.
 11. An LSI design system according to claim 9, wherein saidseparation information generating means generates separation informationwhich sets wirings which generate the change of signals in the equaltiming as said wirings to be separated from signal operation timinginformation of each wiring.
 12. An LSI design system comprising;separation information generating means which extracts wirings to beseparated which are to be arranged in a spaced apart manner from eachother based on the junction number of every wiring, and layoutgenerating means which generates a layout based on said separationinformation.
 13. An LSI design system according to claim 12, whereinsaid layout generating means generates a layout which arranges at leastone wiring which is unnecessary to be separated between said wirings tobe separated,
 14. An LSI design system according to claim 12, whereinsaid separation information generating means sets said wirings whichhave said junction number greater than a preset threshold value as saidwirings to be separated.
 15. An LSI design system according to claim 12,wherein said separation information generating means generates saidseparation information which includes separation distance informationbetween said wirings to be separated.
 16. An LSI design system accordingto claim 15, wherein said separation information generating meansgenerates distance information which is directly proportional to the sumvalue of wiring junction numbers of said wirings to be separated as saidseparation distance information.